Latch circuits are used as basic component circuits of logic circuits in many semiconductor integrated circuits. An arrangement of a conventional latch circuit will be described below.
FIG. 1 is a diagram showing an arrangement of a conventional latch circuit. The latch circuit shown in FIG. 1 is used in applications which require high-speed operation. In the description which follows, bipolar transistors are used as active devices.
As shown in FIG. 1, the latch circuit generally employs a differential logic circuit comprising differential transistor pairs (hereinafter simply referred to as “differential pairs”) for reading and holding data, a differential transistor pair for being supplied with a clock signal and serving to switch currents supplied to the differential transistor pairs in a higher stage, and a transistor as a constant-current source in a lower stage. The circuit arrangement will hereinafter be described in detail below.
The latch circuit has first differential pair (Q1, Q2) for reading a data signal, second differential pair (Q3, Q4) for holding the data signal, third differential pair (Q5, Q6) connected to common emitter point P1 of the first differential pair and common emitter point P2 of the second differential pair, for being supplied with complementary clock signals, and transistor Q7 serving as a constant-current source.
Reference characters 1a, 1b represent data input terminals to which the data signal is supplied and which are connected to the bases of first differential pair Q1, Q2. Reference characters 2a, 2b represent clock input terminals to which the clock signal is supplied and which are connected to the bases of third differential pair Q5, Q6. Reference characters 3a, 3b represent data output terminals for outputting a data signal, which are connected respectively to collectors of first differential pair Q1, Q2 and respectively collectors of second differential pair Q3, Q4. Data output terminals 3a, 3b are connected respectively to the bases of second differential pair Q3, Q4. Reference character 5 represents a high-potential power supply terminal for being supplied with potential Vcc. The collectors of first differential pair Q1, Q2 are connected to high-potential power supply terminal 5 respectively through resistors R1, R2. Reference character 6 represents a low-potential power supply terminal for being supplied with potential Vee. Transistor Q7 has an emitter connected to low-potential power supply terminal 6.
A master-slave flip-flop circuit employing the latch circuit shown in FIG. 1 will be described below. An example of the master-slave flip-flop circuit is shown in FIG. 4 of JP-A No. H05-48402.
FIG. 2 shows an example of the master-slave flip-flop circuit employing the conventional latch circuit shown in FIG. 1. Those parts of the master-slave flip-flop circuit which are identical to those of the latch circuit shown in FIG. 1 are denoted by identical reference characters.
As shown in FIG. 2, a master circuit has the latch circuit shown in FIG. 1 and transistors Q15, Q16. The collector of transistor Q1 of the first differential pair and the collector of transistor Q3 of the second differential pair are connected to the base of transistor Q15. The collector of transistor Q2 of the first differential pair and the collector of transistor Q4 of the second differential pair are connected to the base of transistor Q16. Transistors Q15, Q16 have respective collectors connected to high-potential power supply terminal 5, and respective emitters connected to low-potential power supply terminal 6 through respective resistors R7, R8. Junction 4a between transistor Q15 and resistor R7 is connected to the base of transistor Q4 of the second differential pair, and junction 4b between transistor Q16 and resistor R8 is connected to the base of transistor Q3 of the second differential pair. Junctions 4a, 4b serve as data output terminals of the master circuit. Transistor Q7 has an emitter connected to low-potential power supply terminal 6 through resistor R3.
A slave circuit is of an arrangement identical to the master circuit. As shown in FIG. 2, the slave circuit has fourth differential pair (Q8, Q9) for reading a data signal, fifth differential pair (Q10, Q11) for holding the data signal, sixth differential pair (Q12, Q13) connected to common emitter point P3 of the fourth differential pair and common emitter point P4 of the fifth differential pair, for being supplied with complementary clock signals, transistor Q14 serving as a constant-current source, and transistors Q17, Q18.
The collector of transistor Q8 of the fourth differential pair and the collector of transistor Q10 of the fifth differential pair are connected to the base of transistor Q17. The collector of transistor Q9 of the fourth differential pair and the collector of transistor Q11 of the fifth differential pair are connected to the base of transistor Q18. Transistors Q17, Q18 have respective collectors connected to high-potential power supply terminal 5, and respective emitters connected to low-potential power supply terminal 6 through respective resistors R9, R10.
A junction between transistor Q17 and resistor R9 and a junction between transistor Q18 and resistor R10 are connected respectively to data output terminals 3a, 3b of the slave circuit. Data output terminals 3a, 3b are connected to the respective bases of transistors Q10, Q11 of the fifth differential pair. Junctions 4a, 4b of the master circuit serve as data input terminals of the slave circuit and are connected to the respective bases of transistors Q8, Q9 of the fourth differential pair. Data output terminals 3a, 3b and data output terminals 4a, 4b serve as the output terminals of flip-flop circuit sections.
Operation of the master-slave flip-flop is the same operation of the conventional master-slave flip-flop and will not be described below.